1. Field of the Invention
The present invention relates to a drive circuit of a display device and to a display device, and more particularly to a drive circuit suitable for liquid crystal display devices with a dot inversion drive.
2. Description of the Related Art
Liquid crystal displays are employed as displays for various lightweight and thin electronic devices with low power consumption, such as cellular phones. As liquid crystal displays, a simple matrix type and an active matrix type (AMLCD: Active Matrix Liquid crystal display) using active elements such as TFTs (Thin Film Transistors) in a pixel circuit are known.
FIG. 1 is a block diagram of a well-known liquid crystal display. The liquid crystal display comprises a scanning line drive circuit 2, a liquid-crystal panel 3, a control circuit 7, a data line drive circuit 51, a power source circuit 58, and a common voltage generation circuit 59. Picture signals, vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and dot clock signal dCLK are inputted into the control circuit 7. Power source voltages of VDC and GND are supplied to the power source circuit 58. Gate electrodes of all TFT are connected to the scan lines 5 extending in the row direction, and drain (source) electrodes are connected to the data lines 4 extending in the column direction. Display signals from the data line drive circuit 51 that is controlled by the control circuit 7 are provided to each data lines 4. In such a liquid crystal display, the scanning line drive circuit 2 scans the scanning lines 5 in turn according to the control signals from the control circuit 7, thereby displaying one image on the display (line consecutive method). This one image is called a frame (field).
In the conventional liquid crystal display, the polarity of the voltage applied from the data lines 4 to the pixels via TFT (referred to hereinbelow as “pixel voltage”) is inverted at prescribed periods. In other words, the pixels are AC driven. The term “polarity” used herein indicates whether the pixel voltage is positive or negative with respect to a voltage of a common electrode (com voltage) as a reference. Such a drive method is employed to inhibit the degradation of liquid-crystal material. For example, a dot inversion drive method in which the polarity of pixel voltage is inverted every adjacent data line and scanning line so that the polarity is different for the adjacent pixels, as shown in FIG. 2, and a two-line-dot inversion drive method in which the polarity is inverted for each adjacent data line and every two scanning lines, as shown in FIG. 3, are known. With such drive methods, flickering and other defects are decreased and image quality is improved. The configuration shown in FIG. 4 and described in Japanese Patent Application Laid-open No. 10-62744 has been suggested as a data line drive circuit 51 for realizing the dot inversion drive method. A data line drive circuit 51 comprises a shift register circuit 61, a data register circuit 62, a data latch circuit 63, a switching circuit A 64, a level shift circuit P 65, a level shift circuit N 66, a D/A conversion circuit P 67, a D/A conversion circuit N 68, a switching circuit B 69, a signal processing circuit 70, a positive gradation voltage generation circuit 71, and a negative gradation voltage generation circuit 72. A latch signal STB and a polarity signal POL are inputted into the signal processing circuit 70. A horizontal start signal STH and clock signal CLK are inputted into the shift register circuit 61. The switching circuit A 64 selects the picture signal so as to input it either into the positive polarity drive circuit or negative polarity drive circuit. Further, the switching circuit B 69 switches the outputs from the positive polarity drive circuit and negative polarity drive circuit so that the selected output corresponds to the picture signal.
The positive polarity drive circuit comprises a level shift circuit P 65 for level shifting the picture signal to the positive side with respect to the com voltage and the positive polarity D/A conversion circuit 67. The negative polarity drive circuit comprises a level shift circuit N 66 for level shifting the picture signal to the negative side with respect to the con voltage and the negative polarity D/A conversion circuit 68. A com voltage of 5 V, a positive polarity voltage of from 5V to 10V, and a negative polarity voltage of from 0V to 5V are disclosed as examples of each voltage setting. In this case, the con voltage, the voltage of the data line drive circuit, and the voltage of the scanning line drive are generated by the power source circuit 58.
FIG. 5 is a timing chart showing the relationship between the STB signal, POL signal, and outputs of adjacent data lines 4. As shown in FIG. 5, the polarity of adjacent data lines is inverted and the output of data lines for each frame is inverted. FIG. 6 is a detailed diagram of the switching circuit A 64 and switching circuit B69. It shows the switch state at each timing shown in FIG. 5. As can be understood from FIG. 5 and FIG. 6, the switching circuit A 64 and switching circuit B 69 conduct switching operation so that the output is inverted every line and frame to realize the dot inversion drive.
It has now been discovered that, however, this conventional drive circuit has several drawbacks. The first of them is the increase of circuitry scale. A level shift circuit is provided in each drive circuit corresponding to each data line. If the difference between the voltage inputted into the level shift circuit and the voltage to which the level is shifted is large, the circuitry scale is increased. Furthermore, in the level shift circuit, if the power source voltage is high, it is necessary to increase the breakdown voltage of the elements constituting the circuit. Accordingly, the gate oxide film Tox is made thick, the gate length L and gate width W are increased, and the distance between the elements is increased. As a result, the circuit surface area is increased.
Further, in the conventional drive circuit (FIG. 4), the picture signal of one scanning line is level shifted to a positive or negative side for every two adjacent signals after it has been latched in parallel in the data latch circuit 63. Therefore, if the picture signal is an n-bit signal and the number of data lines is m, then the number of required level shift circuits of each drive circuit is n×m.
Further, in the conventional drive circuit, the signals for every two adjacent signals is switched to a positive or negative level shift circuit 65, 66 after the digital picture signal of one scanning line has been latched in parallel in the data latch circuit 63. Therefore, the number of required switching circuits 64 for switching the digital picture signals is also n×m.
The second drawback is the large power consumption. If the com voltage is 5V, the high level voltage of about 10 V of positive polarity is generated in the power source circuit, as a result, the efficiency of the power source circuit decreases and power consumption increases. A charge pump structure composed of a plurality of capacitors and switches is employed in the power source circuit, and if a voltage of 10V is generated from 2.5V, the power source efficiency is from about 60% to 70%. The switches have a parasitic capacitor, and the power is consumed by this parasitic capacitor, thereby decreasing the efficiency. For example, when the voltage is increased from 2.5V to 5V, the efficiency is 80%, and when the voltage is increased from 5 V to 10 V, the efficiency is similarly 80%, however, for the increase from 2.5 V to 10 V, the efficiency is 80%×80%=64%. If the power source voltage used for drive is high, then the number of voltage increase steps is increased, the efficiency of the power source circuit is decreased, and power consumption is increased.